anwei7208
Joined: 23 Nov 2006
Posts: 13
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 18 Jul 2009 20:21 soc encounter ilm |
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Hi, I'm a beginner. And I'm really frustrated by Cadence encounter user guide.
I'm doing a partitioned design in the bottom-up approach. The sub-blocks have all be placed and routed. Now I need to put them together. The Cadence user guide says:
<<<<After block implementation, an abstract should be developed for each block-level design that will be used in the top-level implementation.
For the bottom-up approach, create a top-level floorplan where block-level abstracts would be referenced in the top-level design. >>>>>
What does it mean? How do I create abstract and how do I refer to them in top level design? The user guide mostly talks about top-down approach. My top design is very simple, but I just can't put them together.
Can any one help me? I'm really desparated.
Thanks very much
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shelby
Joined: 04 Jan 2007
Posts: 76
Helped: 10
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22 Jul 2009 4:00 soc encounter block |
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1) Create a top level verilog where you instanciate and connect all your sub-blocks
2) For each sub-block you need to create the following views.
LEF - for physical information like size, pin locations, blockages, etc ...
Timing View - Either ILM or ETM which end up being in .lib format. This is for timing the IO pins of each block
SI view - Either ECO or cdb model if you are performing noise analysis with CeltIC
3) Load in your top level verilog and LEF/.lib models and you can begin floorplanning at the top level.
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