dc offset problem - need suggestion concerning a circuit

EDAboard.com Forum Index -> Analog Circuit Design -> dc offset problem - need suggestion concerning a circuit

Author

Message

zjrlgf

Joined: 25 Apr 2008
Posts: 12

08 Jul 2009 10:43 dc offset

it is a two stage programmable amplifier, the core amp is an ota, inorder to cancel the dc offset, a feedback loop is adopted. however,
traditional structre(in Razavi's book) can not be used here, because the loop circuit is very sensitive to load.

can anyone give me some suggestion, thanks very much![/img]

Google
AdSense
Google Adsense

08 Jul 2009 10:43 Ads

mengcy

Joined: 21 Aug 2006
Posts: 86
Helped: 6
Location: shanghai

10 Jul 2009 7:41 dc offset problem

I wander whether you drawed the schematic completely.
I designed a fourth order filter with DC offset cancellation.the feedback block acts as a LPF to extract the dc signal of the output. And the BW of the LPF is very low.so the value of R and C is very large.
For the main signal path,the load is only R. when you design the amplifier, This should not be a problem because the R is very large.