Rules | Recent posts | topic RSS | Search | Register  | Log in

Lib and netlist checks - need explanation


Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Lib and netlist checks - need explanation
Author Message
designer_ec



Joined: 31 Mar 2007
Posts: 71


Post04 Jul 2009 10:09   

Lib and netlist checks


Hi,

Before implementing block or full chip we need to some check in given input files.

Please anybody describe detailed about below questions.

1.What are the checks we have to do in given logical libs & physical libs? Please describe detailed about those checks and how to resolve those issues?

2.What are the checks we have to do in given netlist? Please describe detailed about those checks & how to resolve those issues?

3.What are the other checks we need to do? I mean what are the checks we need to do in other i/p files?
Back to top
ljxpjpjljx



Joined: 05 May 2008
Posts: 519
Helped: 12
Location: Shang Hai


Post05 Jul 2009 6:21   

Re: Lib and netlist checks


which appication of your design ?
Back to top
khansal_be



Joined: 04 Jul 2009
Posts: 4
Location: Karachi


Post05 Jul 2009 6:30   

Lib and netlist checks


Hay designer_ec you have not mentioned there which software you are talking about.
first mention that OK
Back to top
Google
AdSense
Google Adsense




Post05 Jul 2009 6:30   

Ads




Back to top
designer_ec



Joined: 31 Mar 2007
Posts: 71


Post05 Jul 2009 17:34   

Re: Lib and netlist checks


Hey this is not related to software or application.I am asking about what are checks need to do in logic & physical libs,netlist & sdc and other input files before we start implement the physical design .
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Lib and netlist checks - need explanation
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
Gate level netlist checks before taking to P and R (3)
what is .lib,LEF,SDC,NETLIST.V,?Plz tell me in detail and wi (3)
question about slow.lib and fast.lib on Design Compiler (10)
need explanation about amplifier and filter (4)
Transistor configuration - need explanation and answers (4)
Need impedance matching explanation and verification (4)
Need explanation of ontology and web semantics (2)
what are hard and soft resets...? need explanation (3)
need the design for this circuit and explanation (1)
check syntax fail error - need help and explanation (1)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS