ludan
Joined: 24 May 2009
Posts: 5
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 03 Jul 2009 10:40 place and route in soce with/without latch |
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Hi guys,
I am facing the following problem since a while: blockA <--> blockB,
at the output of blockA there is a FF and a wire that goes as input to a latch
in blockB.
If I place these two blocks in soc encounter with a certain distance (5mm)
I see a certain delay (~3ns) on the link interconnecting the two blocks.
Now if I replace the latch in blockB with a FF and I place the blocks at the
same distance of 5mm, the delay I see on the interconnection link is 1.7ns
Looking at the timing report, it is clear that using on both sides the FFs,
the tool optimizes the link inferring buffers with a big drive strength.
In the example with 1ff and 1 latch, the buffers inferred are smaller and the
delay is much higher.
Now my question: is there any specific reason why the tool does not recognize
such a long link between A and B as the critical path in case I use a latch?
It is clearly the critical path (as shown by the experiment with 2 FFs), but
for some reason when I use a latch that path is not recognized as critical,
therefore the effort to optimize the link is low and the final interconnection
delay quite high (and disappointing) 
Ideas?
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