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project in System Verilog
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kandaka



Joined: 19 Feb 2007
Posts: 3
Post02 Jul 2009 14:56   

verilog projects
Hi,
I am planing to develop System Verilog environment for any application from
stratch.So,Can anyone suggest me something regarding this.


Thanks in advance.
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jimjim2k



Joined: 17 May 2001
Posts: 1248
Helped: 11
Post02 Jul 2009 18:44   

system verilog projects
Hi

R u mean IDE for systemVerilog?


tnx
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Post02 Jul 2009 18:44   

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sivamani



Joined: 30 Jan 2007
Posts: 28
Helped: 1
Post03 Jul 2009 5:50   

verilog project
Can you pls elabarate further.........
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kandaka



Joined: 19 Feb 2007
Posts: 3
Post03 Jul 2009 7:52   

system verilog project
actually i am new to SV and VMM.So planing to develop the environment for any protocal or DUT so that i can use the main features of SV.

Please suggest me regarding this
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www.testbench.in



Joined: 04 Jun 2008
Posts: 46
Helped: 2
Post27 Jul 2009 14:37   

project verilog
Check out www.testbench.in for SV and vmm complete simple switch example.

If you are interested in developing a environemt for any other protocol, Go to www.opencores.org and verify any rtl. If you found any buy in the rtl, send the bug details to www.opencores.org.
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