SystemVerilog superior for synthesis???

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> SystemVerilog superior for synthesis???

Author

Message

deepa1206

Joined: 12 Jun 2009
Posts: 12

01 Jul 2009 21:33 SystemVerilog superior for synthesis???

Hi

I am trying to understand how SystemVerilog can be more helpful than VHDL/Verilog for designing and synthesizing a circuit. I am aware that it has interface , always_comb, etc which aid in synthesis.

Has anybody synthesized a design coded in SystemVerilog and found substantial improvement in area/power/timing during synthesis in comparison to designs in Verilog/VHDL ? This might be because of the specific language constructs??? Please let me know.

Thanks

Google
AdSense
Google Adsense

01 Jul 2009 21:33 Ads

pmat

Joined: 26 Mar 2007
Posts: 55
Helped: 4
Location: Heraklion, Greece, EU

01 Jul 2009 23:43 Re: SystemVerilog superior for synthesis???

Hi,
i am also interested in high level models
as SV. Can somebody give us any insight of HOW you can formally
verify starting from SV???? (Equivalence Checking???)

Thnx,
Pavlos

ljxpjpjljx

Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai

02 Jul 2009 3:06 Re: SystemVerilog superior for synthesis???

If you write your code within the guideline, it can be synthesised!

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

02 Jul 2009 8:08 Re: SystemVerilog superior for synthesis???

Hi frndz,

Can you tell me if there is going to be any effect on the area or timing in System Verilog w.r.t Verilog??

thanks,
Haneet

hareeshravi

Joined: 06 Sep 2007
Posts: 3

03 Jul 2009 12:42 Re: SystemVerilog superior for synthesis???

Hi,

The language in which you code does not affect the performance of the design. It purely depends on your design, the tool and the library. SV does offers ways to write compact and clear (with less ambiguous) code and also gives immence possibilities for verification.

Please note that coding is done as per the design. It is not the otherway.

Regards,
Hareesh