Sythesis of Finite State Machine (FSM)

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tariq786

Joined: 24 Feb 2004
Posts: 194
Helped: 28

01 Jul 2009 10:38 finite state machine simulator

I have synthesized FSM and data path for a design. When i run the post synthesis gate level Verilog simulation, i get xxxxxxxxx.

I traced the reason and the reason is that in one of the FSM states, i am using "if condition" on an external input (from another module) that does not change in one clock cycle. For example

State_Si:
begin
if(DONE) // DONE (an external signal) takes 10 clock cycles to become true
next_state = State_Sj;
else
next_state = State_Si;
end

So when State_Si is reached the very first time, DONE is neither true nor false. It is unknown. After 10 clock cycles, it becomes 1 and so in these 10 clock cycles, it remains in the state State_Si.

This thing works absolutely fine in pre synthesis behavioral (golden) simulation but does not work after synthesis.

Any ideas how to solve this problem?

Any link or tutorial will be really appreciated.

I hope i made it clear. Let me know if you need more explanation.

Thanks a lot.

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

01 Jul 2009 12:19 unknown states in fsm

i would suggest you to introduce a reset state where you can initially reset all your outputs to 0 and then start the process. this way u can avoid the x and will not have any problem at synthesis

haneet

tariq786

Joined: 24 Feb 2004
Posts: 194
Helped: 28

01 Jul 2009 12:38 Sythesis of Finite State Machine (FSM)

I have done it in the other always block. That is

always@(posedge clk)
if(reset)
current_state <= 0;
else
current_state <= next_state;

Is this what you mean?
What do you mean reset all your outputs? Are you talking about state flip flops like in the above example or what?

Remember i am talking about controlling an external input whose value determines going to the next state or not.

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

01 Jul 2009 13:06 Re: Sythesis of Finite State Machine (FSM)

i meant when u have ur reset make the state_sj=0; along with the other conditions which u mentioned

always@(posedge clk or posedge rst)
being
if(rst)
begin
state_sj<=0;
state_si<=0;
current _state<=....
end

i hope you got what im tryiong to say...

haneet

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tariq786

Joined: 24 Feb 2004
Posts: 194
Helped: 28

01 Jul 2009 18:42 Sythesis of Finite State Machine (FSM)

Let me check and then get back to you.

Thanks again

Added after 5 hours 28 minutes:

No it does not work. States are local parameters in my FSM module and they cannot be put to be equal to 0 as you said i.e.

localparam [5:0] //one hot encoding
S0_INIT = 6'b000001,
S1_FETCH = 6'b000010,
S2_AES = 6'b000100,
S3_CALC = 6'b001000,
S4_WB = 6'b010000,
S5_DONE = 6'b100000;

pmat

Joined: 26 Mar 2007
Posts: 55
Helped: 4
Location: Heraklion, Greece, EU

01 Jul 2009 23:37 Re: Sythesis of Finite State Machine (FSM)

Tariq hi,
apparently some other logic is driving the DONE signal.
can't you initialize this logic to have DONE=0 during these first
10 cycles. It is not a matter of this FSM, as the other logic
is always giving an x as an input...

Pavlos

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

02 Jul 2009 5:50 Re: Sythesis of Finite State Machine (FSM)

tariq can u post the complete code... i guess i will check it frm my end and see wht cld be the problem..

haneet

tariq786

Joined: 24 Feb 2004
Posts: 194
Helped: 28

03 Jul 2009 3:30 Sythesis of Finite State Machine (FSM)

Haneet. Thanks a lot my friend. I have figured out what was wrong.

Have a good one.

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

03 Jul 2009 5:46 Re: Sythesis of Finite State Machine (FSM)

tariq can i also know what was wrong??

tariq786

Joined: 24 Feb 2004
Posts: 194
Helped: 28

03 Jul 2009 8:06 Sythesis of Finite State Machine (FSM)

Sure. The external signal DONE was getting generated after the current state. So its value in the current state was unknown. I made sure that before the FSM reaches the current state, DONE has a valid value of either 0 or 1.

Hope this helps.