array initialization on separate file in verilog

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naz56

Joined: 25 Jun 2009
Posts: 30

30 Jun 2009 18:18 verilog array initialization

hi everyone Smile

can it b possible to initialize array in separate file?
like
/////////////////file(1) define.v //////////
initial
begin

array[0]=8'h56;
array[1]=8'h56;
array[2]=8'h56;
array[3]=8'h56;

end
///////////////////////////////

then in new file named "main.v" i want 2 use "define.v" file here

module kkkk(etc etc);

`include "define.v"

etc etc etc

endmodule

but its nt working...helppppppppppppppppppp

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

01 Jul 2009 11:38 verilog parameter array

yes.. you can do it.. but i dont know about assigning it directly but i have used with the parameter. though the end result turns out the same.

parameter a[0]=3;
rather than a[0]=3;

bye

haneet

naz56

Joined: 25 Jun 2009
Posts: 30

01 Jul 2009 15:52 verilog array

its nt working Sad

anyone there to help???????????

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

02 Jul 2009 5:46 verilog initialize array

are including the define.v in the main .v file??

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02 Jul 2009 5:46 Ads

naz56

Joined: 25 Jun 2009
Posts: 30

02 Jul 2009 5:50 array verilog

YUP HANEET....HELP

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

02 Jul 2009 13:14 how to define an array in verilog code

could you put your code here.. i will see wht the trouble is...

naz56

Joined: 25 Jun 2009
Posts: 30

02 Jul 2009 15:39 verilog array assignment

////////////(main.v) file
module main(out1,out2,in);
output [1:0] out1;
output [1:0] out2;
input in;
reg [1:0]out1;
reg [1:0]out2;

reg [1:0] a[0:1];

`include "define.v"
always @(in)

begin
if(in==0)
out1=a[0];
if(in==1)
out2=a[1];
end

endmodule

///////////////////////////////
module stimulus;
module stimulus();
wire [1:0] out1;
wire [1:0] out2;
reg in;
main mm1(out1,out2,in);
initial
begin

# 10 in=0;
#10 in=1;
#10;

end
endmodule

///////////////////////////////////

2nd file
//////////////////define.v file///////////////
parameter a[0]=2'b01;
parameter a[1]=2'b10;
//////////////////////////////////////

plz check...n how can define.v file is used in main.v file...plz quickly help...i will b very thankful 2 u...

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

03 Jul 2009 5:45 initialize array verilog

hi Naz,

the 1st thing which you should correct is you have declared the array as reg which should be wire since you are initializing the array outside the always block. and another thing don't use parameter...
use `define or simple assign statement.
another thing you have defined stimulus module twice...

Here is the code:
////////////(main.v) file
module main(out1,out2,in);
output [1:0] out1;
output [1:0] out2;
input in;
reg [1:0]out1;
reg [1:0]out2;

wire [1:0] a[0:1];

`include "define.v"
always @(in)

begin
if(in==0)
out1=a[0];
if(in==1)
out2=a[1];
end

endmodule

///////////////////////////////
module stimulus();
wire [1:0] out1;
wire [1:0] out2;
reg in;
main mm1(out1,out2,in);
initial
begin

# 10 in=0;
#10 in=1;
#10;

end
endmodule

2nd file
//////////////////define.v file///////////////
//assign a[0]=2'b01;
//assign a[1]=2'b10;

OR

`define a[0] 2'01;
`define a[1] 2'10;
/////////////////////////////////////////////////

you can use either assign statement or `define. both will work

Haneet

naz56

Joined: 25 Jun 2009
Posts: 30

03 Jul 2009 16:53 using a module in another file verilog

again not working
Crying or Very sad

n output in ModelSim is:

#in=x,out1=x,out2=x
# in=0,out1=x,out2=x
# in=1,out1=x,out2=x

Crying or Very sad

Added after 23 minutes:

hello anybody there 2 help me out?????????????????????????
this is output when using "assign "

in=x,out1=z,out2=z
# in=0,out1=z,out2=z
# in=1,out1=z,out2=z

Added after 48 minutes:

i think when we use `define then there iz no need of `include directive..

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

07 Jul 2009 10:26 verilog include defines.v

hey naz.. i thght i resolved it so didnt check this thread..

whtz the prob u r facing?? the code which i pasted is working perfectly...
i tried it out...

haneet

naz56

Joined: 25 Jun 2009
Posts: 30

07 Jul 2009 10:29 initializing array to 0 in verilog

which simulator u r using? i m using modelsim5.7..but nahi chal raha.. error is macro module iz missing... Sad

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

07 Jul 2009 13:57 initialize array in verilog

i am using vcs....
but i dn tthink there shld be any problem if 1 tool is supporting...
by the way r u using the student version of modelsim??

haneet

naz56

Joined: 25 Jun 2009
Posts: 30

07 Jul 2009 15:27 initialize arrays in verilog

its a cracked version Crying or Very sad

haneet

Joined: 07 Nov 2006
Posts: 149
Helped: 15

08 Jul 2009 5:36 verilog how to put parameters in separate file

i am sure if it has the feature to support the directives...

y dont u try dwnldng the student version and then try??

itz working on my tool so i dnt see y itshldnt work on urs...

haneet