dinesh.4126
Joined: 27 Feb 2008
Posts: 63
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 28 Jun 2009 14:07 hdlparsers:3292 |
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hi,
In I2C Slave Design below are the assignment :
-----------------------------------------------------------------------------
line 367: sda_falling_edge <= true when sda_sampled = "1100" else false;
line 368: sda_rising_edge <= true when sda_sampled = b"0011" else false;
scl_falling_edge <= true when scl_sampled = b"1100" else false;
scl_rising_edge <= true when scl_sampled = b"0011" else false;
----------------------------------------------------------------------------------
and below these are signal declaration :
------------------------------------------------------------------
signal sda_sampled: unsigned(3 downto 0) := (others => '1');
signal scl_sampled: unsigned(3 downto 0) := (others => '1');
signal sda_falling_edge: boolean := false;
signal sda_rising_edge: boolean := false;
signal scl_falling_edge: boolean := false;
signal scl_rising_edge: boolean := false;
-----------------------------------------------------------------------------
below are check syntax fail error.
ERROR:HDLParsers:3292 - D:/iitproject/i2c/i2c/i2c.vhdl Line 367. = has two possible definitions in this scope. For example, parameter 2 (string value) can be: SIGNED or UNSIGNED
ERROR:HDLParsers:3292 - D:/iitproject/i2c/i2c/i2c.vhdl Line 368. = has two possible definitions in this scope. For example, parameter 2 (string value) can be: SIGNED or UNSIGNED
Can somebody suggest me upon why this error is coming even I declare it as unsigned.
Kindly suggest me upon this.
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