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HOW TO IMPLEMENET FOLLOWING EQ. IN VHDL


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koolslash



Joined: 24 May 2009
Posts: 26


Post27 Jun 2009 15:32   

ano ang emotional quotient o eq-tagalog version


(NO. of pulses / total pulses) * 255

then round off the result and convert it to binary.


ANY IDEA OR SOLUTION????
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barath_87



Joined: 07 Feb 2006
Posts: 171
Helped: 10


Post27 Jun 2009 15:39   

vhdl quotient


Can you tell what actually you are trying to implement instead of a math eqn. because your eqn looks odd.
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koolslash



Joined: 24 May 2009
Posts: 26


Post27 Jun 2009 21:19   

vhdl eq


actually i have writen a counter to count number of pulses.
now, i want to:
1. calculate the following:
(no. of pulses counted ÷ total expected pulses) x 255
NOTE: its same like calculating percentage.
2. i have used 255 because it is represented in binary 11111111.
3. this whole equation will give me the pulses percentage from 255.
e.g (20 ÷40) x 255 = .5 x 255 = 127.5
4. now i want to round of this to 127 or 128 any.
5. then convert this result to binary.
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Post27 Jun 2009 21:19   

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linkfox



Joined: 18 Dec 2007
Posts: 52
Helped: 3


Post28 Jun 2009 2:07   

vhdl calculation of percentage


koolslash wrote:
actually i have writen a counter to count number of pulses.
now, i want to:
1. calculate the following:
(no. of pulses counted ÷ total expected pulses) x 255
NOTE: its same like calculating percentage.
2. i have used 255 because it is represented in binary 11111111.
3. this whole equation will give me the pulses percentage from 255.
e.g (20 ÷40) x 255 = .5 x 255 = 127.5
4. now i want to round of this to 127 or 128 any.
5. then convert this result to binary.


you can find implementations for fixed point divisions on-line, on FPGA they provided division IP cores;
but they can only return quotient and remainder, but not 0.5 as u want;
so my suggest would be either do a1 = (total expected pulses/255), then (no. of pulses counted/a1), and take the quotient; or a1 = no. of pulses counted * 255, then a1/ total expected pulses.
also you can use 256 instead of 255 to save one division, since u dont require high accuracy.
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barath_87



Joined: 07 Feb 2006
Posts: 171
Helped: 10


Post20 Jul 2009 17:31   

round binary vhdl


If you are using Xilinx FPGA you can use Xilinx System generator to do this.Just google around for tutorials.If u don't get one then let me know.
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