Verilog simple but bit confusing

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balan

Joined: 18 Feb 2007
Posts: 43

25 Jun 2009 16:32 Verilog simple but bit confusing

Let me know the output of this program

module tb;
reg [15:0] a;
initial begin
a=28'hff00;
$display("a = %h",a);
$display("a = %0h",a);
$display("a = %7h",a);

end
endmodule

balan

Joined: 18 Feb 2007
Posts: 43

27 Jun 2009 5:50 Re: Verilog simple but bit confusing

whether the result which i get is expected.

1st display
ff00
2nd display
ff00
3rd display
ff00

Is that correct

sheik_vb

Joined: 21 Jul 2006
Posts: 63
Helped: 3

27 Jun 2009 8:43 Re: Verilog simple but bit confusing

Yes Correct.

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balan

Joined: 18 Feb 2007
Posts: 43

28 Jun 2009 4:09 Re: Verilog simple but bit confusing

The reg a is 16 bit, but the assignment is a = 28'h ff00 (assigned as 28 bit).

In the display we have given as $display("%7h",a)

I expect the value to be
000ff00.

Please let me know does %7h has any effect.

tiger_cn

Joined: 28 Jun 2009
Posts: 1

28 Jun 2009 8:43 Verilog simple but bit confusing

There must be something wrong with your answer.
you can simular with modelsim and you can see de result are:

1st display
ff00
2nd display
ff
3rd display
___ff00 (_means Space bar)