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how to simulate the slew rate of a fully differential opamp


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foreverloves



Joined: 23 Mar 2006
Posts: 39


Post23 Jun 2009 23:44   

how to simulate slew rate


how to simulate the slew rate or settling time for a fully differential opamp?


How to connect a fully differential opamp to unity gain buffer? thanks
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hanif



Joined: 14 Feb 2007
Posts: 73
Helped: 7
Location: Pakistan


Post24 Jun 2009 7:54   

slew-rate fully-differential opamp unity gain


view this topic, this may help you

http://www.edaboard.com/ftopic112505.html


http://www.edaboard.com/ftopic159349.html


Regards
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kwkam



Joined: 25 Feb 2002
Posts: 299
Helped: 15
Location: Somewhere on earth


Post24 Jun 2009 16:35   

slew rate fully differential opamp


give a step input signal and measure the output signal
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foreverloves



Joined: 23 Mar 2006
Posts: 39


Post02 Jul 2009 23:30   

slew rate


hi, thanks for your reply.

I mean the fully differential opa cannot be connected as non-inverting buffers as single-ended style, so how can i simulate the slew rate of it? thanks
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Post02 Jul 2009 23:30   

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LvW



Joined: 07 May 2008
Posts: 1466
Helped: 242
Location: Germany


Post03 Jul 2009 8:59   

Re: how to simulate the slew rate of a fully differential op


foreverloves wrote:
hi, thanks for your reply.

I mean the fully differential opa cannot be connected as non-inverting buffers......


Why not ?
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rfsystem



Joined: 25 Feb 2002
Posts: 858
Helped: 96


Post04 Jul 2009 9:13   

Re: how to simulate the slew rate of a fully differential op


A fully differential opamp could be connected in a single ended unity gain configuration. That mean that the positive output is only connected to the negative, sometimes called inverting, input. Test signal is driven into the positive input. But that could give sligtly different slew rates.

I opt for applying an unity gain inverting configuration. So four resistors of equal value in symmetric inverting configurations.

The next point is the right amplitude. It should be choosen to overdrive the input stage but not to drive the input stage outside its common mode input range. So that should be considered because most input stages have less input common mode range than output common mode ranges.
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