| Author |
Message |
PigiPigi
Joined: 01 May 2002
Posts: 49
|
 20 Jan 2003 5:48 Synthesize Ram? |
|
|
|
I want to write a vhdl code for a static ram, that every fpga synthesize tools extracts it and uses avilable ram in fpga instead it. Anybody can provide usefull information?
PigiPigi,
|
|
| Back to top |
|
 |
frankchen00
Joined: 25 Dec 2002
Posts: 20
|
| 20 Jan 2003 5:53 |
|
|
|
1. Choose the RAM type that you want.
2. Specify the RAM size.
3. Replace the RAM into your design.
|
|
| Back to top |
|
|
ntxp
Joined: 29 May 2002
Posts: 57
|
| 20 Jan 2003 6:03 |
|
|
|
if u want to use vhdl to describe a static ram for a fpga, you could explicitly instantiate the fpga's ram primitive, like blockRAM in Xiline.
if you want to use vhdl to describe a static ram for any type of fpga that use its primitves, I think you have problem doing it in a single description. Every synthesizer will infer SRAM in a bit different manner. If you don't care the to optimise the use of fpga's primitive, you could always write a SRAM description in VHDL and let the synthesizer to implement it using LUTs, however, it is not recommended for large SRAM size as it consumes too much LUTs that would be used for other uses.
ntxp
|
|
| Back to top |
|
|
cuiyujie
Joined: 25 Apr 2002
Posts: 26
|
| 20 Jan 2003 8:30 |
|
|
|
| Simply write a behavioral array and write processes to define its rd/wr method, 1/2 port, etc. the synthesizer in FPGA will convert it to its own RAM, of course sometimes have performance degrade when it doesn't fit in the original one.
|
|
| Back to top |
|
|
linuxluo
Joined: 26 Jul 2002
Posts: 511
Helped: 4
|
| 21 Jan 2003 4:34 |
|
|
|
Hi,
If you want to use VHDL code to synthesis RAM , FPGA must convert it to its own RAM . And even if not converted, your result is not RAM, just Flipflop array.
|
|
| Back to top |
|
|
Al Farouk
Joined: 13 Jan 2003
Posts: 195
|
| 21 Jan 2003 12:55 |
|
|
|
| writing VHDL code that descibe ram is possible for some synthesizers as (Leonardo) but from experince it consume large area. The best way to save area and achive fast design is to instatiate RAM that the vendore supply.
|
|
| Back to top |
|
|
linuxluo
Joined: 26 Jul 2002
Posts: 511
Helped: 4
|
| 21 Jan 2003 13:16 |
|
|
|
Hi, Al
I think whatever synthesis tool you use,such as synopsys dc, cadence ambit etc. ,you can't get RAM result from RTL. If you want a RAM ,you have to get suport from library vendor or foundry vendor and using silicon compiler tools specific to vendor.
|
|
| Back to top |
|
|
frankchen00
Joined: 25 Dec 2002
Posts: 20
|
| 21 Jan 2003 13:17 |
|
|
|
I think that I do not mention clearly in the previous post.
First, You could write HDL to describe your RAM.
But the best way is to write according to a standard RAM style.
(For example, single-port RAM or two-port RAM)
Then, in FPGA, try to find the RAM that FPGA had provided to replace
the RAM that your design.
If you have the "Memory Compiler" (provided by the Fundry Vendor),
you could generate the HDL code for RAM directly from the compiler.
|
|
| Back to top |
|
|
Nobody
Joined: 04 Oct 2001
Posts: 250
Location: Formosa
|
| 21 Jan 2003 17:12 |
|
|
|
| The common IP provider deal the ram instantiate with wraper . That make you compile your IP both in asic and fpga enviroment more friendly.
|
|
| Back to top |
|
|
Agent006
Joined: 12 Feb 2002
Posts: 39
|
| 21 Jan 2003 22:25 |
|
|
|
| I have synthesized this VHDL code for RAM in a Xilinx FPGA
|
|
| Back to top |
|
|
Agent006
Joined: 12 Feb 2002
Posts: 39
|
| 21 Jan 2003 22:28 |
|
|
|
| Don't know why it didn't attached the file..however here it is again
|
|
| Back to top |
|
|
Agent006
Joined: 12 Feb 2002
Posts: 39
|
| 21 Jan 2003 22:29 |
|
|
|
LIBRARY ieee;
USE ieee.std_logic_1164.ALL, IEEE.Std_logic_arith.all;
ENTITY ram_nxm IS
Generic(n: Positive:=3; m: Positive :=4);
PORT(address : IN Unsigned(n-1 DOWNTO 0);--unsigned is one dimensional array of values of type std_logic i.e. they effectively are std_logic_vector
Enable, RW: IN STD_LOGIC;
data : INOUT Unsigned(m-1 DOWNTO 0));
END ram_nxm;
ARCHITECTURE version1 OF ram_nxm IS
BEGIN
PROCESS(address, Enable, RW, data)
TYPE ram_array IS ARRAY (0 TO 2**n-1) OF Unsigned(m-1 DOWNTO 0); --This type is defined as Unsigned in numeric_std
VARIABLE index : INTEGER := 0;
VARIABLE ram_store : ram_array;
BEGIN
IF Enable = '1' THEN
IF RW = '0' THEN
--write to ram on rising edge of write pulse
ram_store(conv_integer(address)) := data;
ELSIF RW = '1' THEN
data <= ram_store(conv_integer(address));
ELSE
data(I) <= (Others => 'Z');
END IF;
ELSE
data(I) <= (Others => 'Z');
END IF;
END PROCESS;
END version1;
|
|
| Back to top |
|
|
