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How to implement a PLL lock detector?
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DZC



Joined: 12 Sep 2006
Posts: 158
Helped: 11
Post24 May 2009 13:03   

pll lock detector
Is there any common used method?
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E-design



Joined: 01 Jun 2002
Posts: 947
Helped: 68
Post26 May 2009 17:52   

pll lock detection
Do you want just a indication when lock is achieved, like a circuit with a LED?
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taotaohai



Joined: 28 Nov 2008
Posts: 4
Post17 Jun 2009 9:58   

lock detector
start from the point before VCO,the voltage is a fine detector point.
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zorro



Joined: 06 Sep 2001
Posts: 380
Helped: 47
Post17 Jun 2009 13:32   

up down signal pll
Hi,

A good method is to use a second phase detector (PD) that compares the phase of the incoming signal with the VCO shifted 90 degrees.

When locked, the (filtered) output of this second PD is a DC.
Without input signal, the output is zero (or noise if the input is just noise).
When unlocked, the output oscilates with zero mean (no DC).
So, a low-pass filter followed by a threshold comparator gives the lock indication.

Regards

Z
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rania_hassan



Joined: 29 Apr 2005
Posts: 109
Helped: 8
Location: Egypt
Post02 Jul 2009 12:50   

how pll locked
Hi, you can use XOR for the Up and Down signals and take the out after certain delay time
if we have lock, the Up and Down signal are the same
Best regards,
Rania
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rfsystem



Joined: 25 Feb 2002
Posts: 858
Helped: 96
Post04 Jul 2009 9:17   

pll mit xor
As Rania point out use an XOR of UP and DOWN than make an RC-lowpass of the XOR ouput and compare to fraction of logic supply. Locking means to stay within a phase difference which is the fraction of the lowpass filtered XOR.
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zoujunjx



Joined: 13 May 2004
Posts: 53
Post17 Jul 2009 5:09   

lock detect pfd up down
I also need a pll lock detector, could anyone provider some papers or some schematic diagrams? Many thanks in advance!

To rania_hassan,
Up and Down signals could not be exactly same in practice. If using XOR gate, it might generate wrong message. How to avoid it?

To rfsystem
What's mean the fraction of digital supply? Do you mean that the filtered outpuf of XOR is compared to a reference voltage, which is e.g. 0.5*VDD ? Please correct me if I misunderstood.
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rania_hassan



Joined: 29 Apr 2005
Posts: 109
Helped: 8
Location: Egypt
Post20 Jul 2009 12:22   

pll lock detector
To zoujunjx
Up and Down signals are exactly the same if you use PFD
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