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spectre_man
Joined: 12 May 2009
Posts: 2
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 13 May 2009 16:54 trace impedance |
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Hello,
I have a multilayer board (12 layers, might have to increase...read on) with multiple isolated grounds (returns).
It is an FPGA design, and all of the signals with critical impedance specs are FPGA-ground referenced digital I/O signals.
In my layer stackup, there are six pwr/gnd plane layers, but only one of these is FPGA-GND. It is a true plane layer (takes up entire board area).
The impedance calculations I'm getting from board vendors seem to be measuring the thickness of the dielectric between a signal on layer N and the NEAREST plane layer(s), not to the FPGA-GND layer to which the signal is referenced, even if that nearest plane layer(s) is (are) totally isolated from the signals in question. Does that make any sense?
If not, how should this be done? I imagined (perhaps incorrectly) that the trace WIDTH would be varied on each layer so that the impedance calculation (using the width on that layer, and the separation distance from the FPGA-GND layer) would come out to the spec (in this case 50 Ohm). If this is the case, that should be fairly simple. Is the impedance calc changed at all by the fact that there may be isolated metal plane layers between the critical trace and its reference plane? I can't find any trace impedance model that shows this, but in the real world on a multilayer board it seems crazy to require that the gnd plane (reference) always be adjacent to a routing layer containing signals referenced to that ground--every other layer would have to be a ground layer.
thanks,
Jude
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senilicus
Joined: 26 Feb 2007
Posts: 87
Helped: 12
Location: The Netherlands
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14 May 2009 6:54 trace impedance reference layer |
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Each interconnect is a transmission line with a signal and a return path, regardless of its lenght, shape or signal rise time. A signal sees a instantaneous impedance at each step along its way down an interconnect.
For 'fast' signals, the return path will be as close as possible to the signal path. This will be the plane that is closest to the signal path. For the return path it doesn't matter if the plane is a GND or VCC plane.
If you want to reference a plane that is further away, then you have to remove the planes underneath the trace in such a way that the required reference plane is the closest plane to the signal. Normaly you dont want to 'open" planes, you want them as solid as possible.
The smaller the loop, the less SI problems you will have. If you want to reference the FPGA GND layer only, move this layer adjacent to the signal layer.
There are a lot of books covering this issue like;
Eric Bogatin - Signal Integrity Simplified
Douglas Brooks - Signal Integrity Issues and Printed Circuit Board Design
Stephen thieraf - High Speed Circuit Board SI
Howard Johnson - High Speed Digital Design, A handbook of black magic.
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spectre_man
Joined: 12 May 2009
Posts: 2
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14 May 2009 21:45 layer adjacent trace pcb |
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Thanks--I just spoke to Prof. Tom Van Doren (the master of all grounding/shielding issues) at Missouri Institute of Science and Technology, and he confirms what you said. I didn't understand the reasoning, but he made it very clear. The reason is because for high frequency, the capacitive coupling between the plane layers looks like a short, and so the return currents DO follow the electrically isolated planes, as they are closer to the signal stripline, and so present the lowest impedance.
Thanks!
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