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How to remove the delay from the output of DPLL(Urgent)
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jawadysf



Joined: 27 Nov 2008
Posts: 9
Post03 Apr 2009 23:40   

How to remove the delay from the output of DPLL(Urgent)
I am recovering the clock from the DPLL as manchester data as input to the DPLL.But when i implemented the DPLL on SPARTAN3 Board,output clock exhibits a delay from the input clock.
Can anyone suggest that how to remove this delay?
Its urgent

Thanks
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Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> How to remove the delay from the output of DPLL(Urgent)
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