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rewkie
Joined: 02 Dec 2002
Posts: 10
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 18 Jan 2003 7:37 Synchronous/Asynchronus Reset? |
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| Synchronous/Asynchronus Reset?
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sunjimmy
Joined: 10 Jan 2003
Posts: 138
Helped: 2
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| 20 Jan 2003 3:05 |
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If the edge of reset signal is synchronized with system clock edge, it's synchronous reset. Otherwise it's asynchronous reset.
Hope it clarify the difference 
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flatulent
Joined: 19 Jul 2002
Posts: 4856
Helped: 292
Location: Middle Earth
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| 20 Jan 2003 3:09 level too |
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| For level resets, async has the reset when the level is reached. in sync reset the level has to be there at least as long until the next clock comes along and the reset is done then. In both, the level has to stay there for a certain time after the reset or unusual things may happen.
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ted
Joined: 12 Mar 2002
Posts: 118
Helped: 3
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| 20 Jan 2003 3:39 |
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I guess everything was said by sunjimmy and flatulent, but the things are always better to explain in more views, so that the practical consequences became completely clear:
Asynchronous reset (often also caller "clear") does reset /clear the state imediately, independently of the clock edges. It usually overrides any clock-synchronized actions, so it keeps the system/component firmyin "reset-state" while active.
Synchronous reset is always related to the clock active edge. It is for a register equivalent of loading with "reset-value" - usually zeros. It has no effect outside the active clock edge (just be aware setup and hold times around the edge -see below).
The sister functions: synchronous preset / asynchronous preset behave similarly, except they set a register's value (usually) to "1" instead of "0". Thus the asynchronous one is more powerul than the synchronous one and always immediate in it's action.
As flatulent points out, having pulses too narrow and not respecting setup time/hold time for the synchronous signal, may lead to something called metastability, and the consequences can be quite unexpected, and completely unpredictable. Therefore, if the synchronous reset/preset is not stable at/near the clock edge (i.e. stable before "setup time" or until "hold time"), or the pulse is shorter than the data sheet minimum, be aware! The result will not be predictable nor reliable.
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linuxluo
Joined: 26 Jul 2002
Posts: 511
Helped: 4
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| 20 Jan 2003 3:58 |
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Hi,
I think in ASIC design, use Asyn reset or syn reset is mostly depend on library cell. Normally, register cell in standard library is asyn reset, so you had better to use asyn reset. But be careful the race condition happed.
But syn reset is good if your library has syn reset register.
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Laplace
Joined: 26 Feb 2002
Posts: 122
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| 20 Jan 2003 5:26 |
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Hey Guys,
How about "high" or "low" reset? what is the critical point here while deciding for "high" or "low" ?
Thanks
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flatulent
Joined: 19 Jul 2002
Posts: 4856
Helped: 292
Location: Middle Earth
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| 20 Jan 2003 5:40 preset and clear |
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| Some have only clear others have clear and preset inputs. It is all a matter of what your overall circuit needs. For instance, if you are making a timer, the circuit is set to all zeros (clear) before the timing starts. Some counters have a load input so that it can be set to a specific value. The loads can be sync or async. A common divide by N system loads a given number and counts down. When the count reaches all zeros, the borrow is fed around to load.
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steshenko
Joined: 31 May 2002
Posts: 67
Helped: 1
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| 20 Jan 2003 11:10 About HIGH and LOW reset |
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| Several decades years ago the TTL logic was a most popular. In HIGH output power consoption was less then out is LOW - traditionally reset and other short sygnals are LOW. But now it is only designer decision and consideration - you can use a HIGH level for reset or LOW as you want
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linuxluo
Joined: 26 Jul 2002
Posts: 511
Helped: 4
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| 21 Jan 2003 4:07 |
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Hi ,
I think the high reset or low reset is depend on the standard cell library you use. If in library there only exist flipflop have low reset pin , so you had better use low reset ,otherwise you have to use a unnessesary NOT cell.
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windflower
Joined: 17 Jul 2001
Posts: 98
Helped: 1
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| 21 Jan 2003 8:17 |
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wish this paper can help you.
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chwpark
Joined: 01 Jan 1970
Posts: 26
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| 21 Jan 2003 20:29 |
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Async RST:
if(rst = '1') then
sig1 <= '0';
elsif(clk'event and clk = '1') then
..........
Sync RST:
if(clk'event and clk = '1') then
if(rst = '1') then
sig1 <= '0';
else
.......
end if;
Notice 'rst', 'sig1' and 'clk'.
Do you understand?
good luck
chwpark
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fivaro1
Joined: 26 May 2001
Posts: 50
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| 21 Jan 2003 22:31 |
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Always supposing that clock is present. What about if it dissapears?
I personally prefer using asynchronous reset. But I just design with FPGAs, perhaps it`s not the same context...
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Phytex
Joined: 16 Dec 2001
Posts: 176
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| 22 Jan 2003 0:48 Reset |
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In the most Designs you use a asynchronus reset and a synchron design.
If you use asynchronus busses like a VME-Bus you need to synchronize them for your Design!
Asynchronus Designs are complicated to handle, because you can have delays between signals!!
Phytex
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fivaro1
Joined: 26 May 2001
Posts: 50
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| 22 Jan 2003 0:59 |
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I agree with you Phytex: I also use asyn. rst and sync design. The few times I had to include asynchronous parts in my designs, all were problems until I developed synchronizers able to communicate async. logic with the synchronous one. Timing analysis was quite critical.
Regards
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