electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

Digital Phase Lock Loop Design
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Digital Phase Lock Loop Design
Author Message
jawadysf



Joined: 27 Nov 2008
Posts: 9
Post24 Mar 2009 17:14   

Digital Phase Lock Loop Design
Hello Frendz

I want to extract the clock from the Manchester coded input data ,i have tried to implement the different techniques of ADPLL but i didn't get the exact result.
Can anyway suggest the working model or any type of solution to this problem.?
Back to top
Aya2002



Joined: 12 Dec 2006
Posts: 1409
Helped: 254
Location: Iraq
Post24 Mar 2009 17:40   

Digital Phase Lock Loop Design
i am not interest in simulink but i can say that you can go to the matlab groupnews website. I am sure you will find the solution. As well, may be my friend will help you, his username is communication_engineer. I will ask him now.

Regards
Back to top
Google
AdSense
Google Adsense
Post24 Mar 2009 17:40   

Ads


Back to top
FvM



Joined: 22 Jan 2008
Posts: 5161
Helped: 767
Location: Bochum, Germany
Post24 Mar 2009 17:45   

Re: Digital Phase Lock Loop Design
Quote:
i didn't get the exact result
What are your results?
Do you have a suitable oversampling reference clock? Also, if you want the PLL clock to be in phase with the bit clock without a 180° ambiguousity, it must take part in the synchronizing mechanism, e.g. decode the preamble or sync characters used in your link. A state machine decoding the manchester signal gives both, clock and data.
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> PLD, SPLD, GAL, CPLD, FPGA Design -> Digital Phase Lock Loop Design
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
phase margin of phase lock loop (4)
Phase lock loop (3)
phase lock loop (7)
Phase lock loop in simulink (5)
how to use a phase lock loop (2)
PLL / Phase Lock Loop Controller (1)
reference oscillator for phase lock loop (1)
phase lock loop locking but not at desired frequency (8)
Costas Loop - loop filter bandwidth + capture & lock ran (4)
reference oscillator for phase loked loop design (13)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS