Native device layout problem

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santhua

Joined: 24 Jan 2008
Posts: 8

19 Mar 2009 7:20 Native device layout problem

Hi,

Why is that native nmos transistor cannot be placed within a Deep nwell.
I have a case in which the whole analog ckt is placed within a Deep nwell but I am not able to place a Native mos.
I am using UMC65.

Thanks in Advance.

erikl

Joined: 09 Sep 2008
Posts: 737
Helped: 139
Location: Germany

19 Mar 2009 15:39 Re: Native device layout problem

santhua wrote:

Why is that native nmos transistor cannot be placed within a Deep nwell.

I guess, because it wouldn't create a native nmos, but a depletion NMOSFET. Vth would change a lot.
And there's probably no simulation model available for this.

mdcui

Joined: 23 Aug 2005
Posts: 110
Helped: 22
Location: China shanghai

24 Mar 2009 1:55 Native device layout problem

n-mos device placed in deep n-well is called tripple well N-device, best usage is to pass negative voltages efficiently or overcome the body effect as a current-passing device.. as for the Vt or other performance parameter, it all depend on processing, may or may not be depletion type. in our design, we use Deep-Nwell Nmos device a lot, generally they have similar performance compared to native N-mos.

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erikl

Joined: 09 Sep 2008
Posts: 737
Helped: 139
Location: Germany

24 Mar 2009 11:39 Re: Native device layout problem

mdcui wrote:

So you probably think of the Isolated NMOS device referenced by item 9.2 in the figure below:

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mdcui

Joined: 23 Aug 2005
Posts: 110
Helped: 22
Location: China shanghai

24 Mar 2009 12:54 Native device layout problem

yes, the isolated NMOS is exactly the one that I mentioned, we called Deep-Nwell NMOS device. and use it widely in our design.

evi

Joined: 29 Nov 2005
Posts: 26
Helped: 1
Location: Canada

04 Nov 2009 4:18 Re: Native device layout problem

santhua wrote:

A native nmos is made by depositing the gate oxide directly on the lightly-doped substrate. A normal nmos is made by an p-implant into p-substrate so that a higher-doped area below the gate is formed (so-called p-well) which increases the threshold voltage. When isolated nmos is made, a deep nwell is created by n-implant in the substrate, and then a higher-doped p-implant is placed on top of the nwell to form a p-well for nmos- this is the same implant that is used to form a pwell for normal nmos. So there is no way to form a native nmos in deep nwell, because you would need a special lightly doped area in the deep nwell for that which is very difficult to do, probably not possible, because the doping concentration and profile would have to mach very closely that of the deep nwell, but would need to be shalower.

However medium vt device can be formed in deep nwell, although this option is usually not provided by most foundries.