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Help PLZ!! FPGA Clock- creating a clock from the input clock
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fallingrain_83



Joined: 24 Jul 2005
Posts: 17
Location: USA
Post04 Mar 2009 18:45   

Help PLZ!! FPGA Clock
Hi all
I want to creat a clock from the input clock that has less frequency
I tried this, however it is not working
module(clk,...)
input clk; // connected to C9 pin of Spartan3 XC3S200
reg [0:25] count;
reg clk2;

allways @(posedge clk)
begin
count<=count + 1;
clk2 <= count[25];
end

allways @(clk2)
begin
clk2<=0;
,.....
end
Crying or Very sad
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FvM



Joined: 22 Jan 2008
Posts: 5161
Helped: 767
Location: Bochum, Germany
Post04 Mar 2009 19:39   

Help PLZ!! FPGA Clock
If you remove the second always block, the design should basically work as a 2**26 clock divider.
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Post04 Mar 2009 19:39   

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fallingrain_83



Joined: 24 Jul 2005
Posts: 17
Location: USA
Post04 Mar 2009 20:30   

Help PLZ!! FPGA Clock
but I have to do s.th in my always block
if I remove that I have to chek clk2 by if and I have an error with this syntax:
lways @(posedge clk)
begin
count <= count + 1;
clk2 <= count[25];
end;

if (clk2) //// ERROR:line 49 expecting 'endmodule', found 'if'
begin

clk2 <= 0;
if (i<9)
begin
if (num[i]>num[i+1])
begin
temp<=num[i];
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FvM



Joined: 22 Jan 2008
Posts: 5161
Helped: 767
Location: Bochum, Germany
Post04 Mar 2009 22:27   

Help PLZ!! FPGA Clock
At least you have to remove clk2 <= 0, it's causing a multiple source error otherwise. The reg clk2 can be set in one always block only. Missing endmodule is another issue of course. You showed just some snippets, I didn't check the overall syntax, but it has to comply with Verilog rules as well.

I you think, clk2 <= 0 is meaningful for your code, you have to redesign the first always respectively. You can use multiple concurrent assignment inside an always block (the last wins), so it would be possible within the first one.
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yanzixuan



Joined: 26 Feb 2009
Posts: 18
Helped: 1
Post05 Mar 2009 5:10   

Re: Help PLZ!! FPGA Clock
Quote:

but I have to do s.th in my always block
if I remove that I have to chek clk2 by if and I have an error with this syntax:
lways @(posedge clk)
begin
count <= count + 1;
clk2 <= count[25];
end;

if (clk2) //// ERROR:line 49 expecting 'endmodule', found 'if'
begin

clk2 <= 0;
if (i<9)
begin
if (num[i]>num[i+1])
begin
temp<=num[i];

if can only be used in "always" or "initial" block in RTL.
if you want to do that ,you can use "assign";
for example:
Code:

wire a,b;
assign a = (b) ? 1: 0;

it equal to:
if(b == 1)
a = 1;
else
a = 0
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