How to use PLL to generate off-chip clock divider circuit?

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nooby_rat

Joined: 02 Dec 2008
Posts: 3

24 Feb 2009 12:20 pll +excel sheet

How should I generate such a divide by 96 clk externally, that is in phase with the source clk?

Is it possible for an off-chip PLL to do the job? And how should i go abt doing that?

Thanks!!

Last edited by nooby_rat on 27 Feb 2009 5:15; edited 1 time in total

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Digital-L0gik

Joined: 26 Jan 2009
Posts: 37
Helped: 1

24 Feb 2009 22:19 clock divider circuit

An off chip pll does not sound like a good idea. You have a single PLL to generate your refclk and thats all you really need. You can divide that clock down as you see fit using conventional methods. To minimize skew, phase offsets, you must use your clock buffers/trees to distribute the divided clock to the destination. Additionally you might want to consider that PLL's typically have multiple clock outputs that can be at different frequencies. Play with the pll configuration dividers to obtain your 1.5 Mhz clock on one output and then try to get some other output to be as close to your 16KHz as possible. This will allow you to simplify the complexity of your clock divider circuitry. Use an excel sheet to help you manipulate the pll formula. Also read the data book to see that your configuration is within the VCO frequency range to ensure minimal skew on the output clocks. Good luck.