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SystemVerilog - random testbench for a mux?
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brenox



Joined: 26 Nov 2008
Posts: 7
Post09 Feb 2009 18:31   

SystemVerilog
Hi, I'm trying to do a random coverage of a serial. For this I'm first trying to do a testbench for a mux 2:1. Actually I've already did a testbench of this, but I'm not getting it right when I try to make it random.

Does anyone know how to do a random testbench for a mux?

Thanks.
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www.testbench.in



Joined: 04 Jun 2008
Posts: 46
Helped: 2
Post11 Feb 2009 10:01   

Re: SystemVerilog
I attached a ones counter example. It demonstrates cover group and assertion coverage.

Find the attachment.


For more infomation

www.testbench.in

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