Leonardo Spectrum Clock Constraint Effect

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bozdas

Joined: 07 Apr 2006
Posts: 7

29 Jan 2009 13:06 Leonardo Spectrum Clock Constraint Effect

Hi,

i have synthesized my work in LS with and without clock frequency constraint,
i had different delay reports (smaller delay with constraint),

is this really effects the synthesis every time or specific situation for my design?

another question is about terms "delay" and "latency":
are these terms different?

thank you

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raki31

Joined: 11 Oct 2008
Posts: 57
Helped: 3

30 Jan 2009 6:03 Re: Leonardo Spectrum Clock Constraint Effect

Without design frequency how can u proceed to next stages!!! V have to constraint clock definitely........

we have two types of Latency..... source latency and network latency

delay from root is network latency.
delay from source point is source latency..

thanku

bozdas

Joined: 07 Apr 2006
Posts: 7

30 Jan 2009 10:36 Re: Leonardo Spectrum Clock Constraint Effect

Hi raki31,

thank u for your reply,

sorry for a missing information about my design,

my design is a combinational cct. so i dont have a clock signal,

specifying a clock constraint seemed weird to me first,
but when i tried to use constraint i got smaller delay,

do we have to constraint clock in even combinational designs?

thank u

raki31

Joined: 11 Oct 2008
Posts: 57
Helped: 3

30 Jan 2009 16:28 Re: Leonardo Spectrum Clock Constraint Effect

u mean to say ur design does not contain sequential elements........?

If this is the situation A Design with no sequential elements have to be constrained virtually..... in constraint file u need to define virtual clock for pure combinational circuit....

Thanku Very Happy