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include file in verilog
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senddilu



Joined: 15 Apr 2006
Posts: 14
Post01 Jan 2009 7:31   

verilog include file
For including a file in verlog, i used `include in a test module. So my aim
was to call the tasks that are defined in the file 'include "task_def.v"
while compliling, i have tried compiling both the test module and task_dev.v
Modelsim is reporting lots of errors for the variables declared in the files.
How to get rid of the problem.?
-Thanks
Senddilu
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HolySaint



Joined: 31 Aug 2008
Posts: 136
Helped: 3
Post01 Jan 2009 13:55   

verilog include
only compiling the file which includes the task file is ok
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Post01 Jan 2009 13:55   

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ljxpjpjljx



Joined: 05 May 2008
Posts: 533
Helped: 12
Location: Shang Hai
Post02 Jan 2009 6:42   

include files in verilog
also you should add some option!
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