kimjin
Joined: 06 Mar 2005
Posts: 62
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 14 Dec 2008 13:31 when will the wr_almost_full be set to "1" in this |
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always @(posedge clk_wr or negedge rst_n)
if (~rst_n)
wr_almost_full <= 1'b0;
else if (reset_fifo_wr)
wr_almost_full <= 1'b0;
else if (wr)
begin
// set full bit a bit early to allow for the fact that the master
// will sample it whilst data is still streaming back on Avalon
if (wr_used > ({WR_PTR_WIDTH{1'b1}} - 8 ) - (1 << (WRITE_ALMOST_BIT - 1)))
wr_almost_full <= 1'b1;
end
else if (wr_almost_full)
begin
if (wr_used > ({WR_PTR_WIDTH{1'b1}} - 8 ) - (1 << (WRITE_ALMOST_BIT - 1)))
wr_almost_full <= 1'b1;
else
wr_almost_full <= 1'b0;
end
WR_PTR_WIDTH=7
WRITE_ALMOST_BIT =6
i think the wr_almost_full will set when wr_used >110,
but it set when wr_used >96,
why it's 96 but not 110, any suggestion is welcome.
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j_andr
Joined: 30 Mar 2008
Posts: 107
Helped: 20
Location: europe
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15 Dec 2008 17:16 Re: when will the wr_almost_full be set to "1" in |
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I've done such simple test code:
| Code: |
module shift_test
(
input clk,
output reg [6:0] tmpA, tmpB,
output reg [6:0] wr_used
);
parameter WR_PTR_WIDTH = 7,
WRITE_ALMOST_BIT = 6;
always @(posedge clk)
begin
tmpA <= ({WR_PTR_WIDTH{1'b1}} - 8 );
tmpB <= (1 << (WRITE_ALMOST_BIT - 1));
wr_used <= ({WR_PTR_WIDTH{1'b1}} - 8 ) - (1 << (WRITE_ALMOST_BIT - 1));
end
endmodule |
after compilations I got such - as expected - numbers:
tmpA = [dec] 119, 1110111
tmpB = 32, 100000
wr_used = 87; 1010111
---
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