Constrained Random Testing and Directed Testing

EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Constrained Random Testing and Directed Testing

Author

Message

vlsi_whiz

Joined: 12 Nov 2005
Posts: 171
Helped: 24

20 Oct 2008 9:33 Constrained Random Testing and Directed Testing

Hi,

Could anyone tell me what Constrained Random Testing and Directed testing are in Verification. Could you also tell how we generate the Test vectors/cases for these tests.

Google
AdSense
Google Adsense

20 Oct 2008 9:33 Ads

viju

Joined: 26 Nov 2006
Posts: 60
Helped: 8
Location: Bangalore

20 Oct 2008 14:29 Constrained Random Testing and Directed Testing

Directed testcases are the testcase, where you generate the fixed pattern and knowingly a scenario that hits a specific features or line of the code. That means that testcase could hit that part only.
While in directed random testing, you have a mechanism created in your Verification environment such that you can randomize the things which is under control. Say you generate the 32 (constrained) packets in which random data (randomness) is stored. Or you can generate the packet with random sizes and random length.

Generally verification is done with the random scenarios , but while your random scenario is not able to hit the particular scenario or pattern, which results in low coverage, you go for directed testing. Initial smoke testcases are also directed testcases.
Hope this helps......