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dexter_ex_2ks
Joined: 19 Jun 2006
Posts: 33
Helped: 1
Location: Romania
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 06 Oct 2008 14:51 New in Digital design and synthesis...some questions I have. |
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Hello everyone 
I have a few questions regarding Digital Synthesis. I know that synthesis can be done in Synopsys (this is one way, there are more) . What is the difference between Design Analyzer and Design Compiler? Is someone included in the other? For what is one and for what is the other? And for what is VCS ? And ISE for? Which one is for RTL coding, synthesis, simulation, verification, and probably layout.
Thanks in advance.
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viju
Joined: 26 Nov 2006
Posts: 52
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Location: Bangalore
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| 06 Oct 2008 15:54 New in Digital design and synthesis...some questions I have. |
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Hi,
1.
Disign vision is GUI based version of DC. DC includes Design vision. May be GUI based tool is not that powerful as DC command line version.
2.
VCS, is a simulato from Synopsys. It supports verilog, VHDL and all most all HVLs (hardware verification languages... like System Verilog, System C, Vera, c based interface... and in future 'e')
3.
ISE is from Xilinx Inc. It is used for synthesis, P&R and bitstream generation for Xilinx FPGAs and CPLDs. While DC can be used for ASIC (i.e. based on libaries) and DC -FPGA for FPGA only for supported vendors(e.g. xilinx , @ltera etc.) and supported devices.
4.
No tool is required for RTL coding... you have to type the code in any editors.
For synthesis, I already mentioned above. For verification (functional) and simulation VCS is use.
hope this helps.....
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dexter_ex_2ks
Joined: 19 Jun 2006
Posts: 33
Helped: 1
Location: Romania
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| 06 Oct 2008 16:26 Re: New in Digital design and synthesis...some questions I h |
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Thank you very much, for your answer.
So ISE is from Xilinx, I understood. Actually a wanted to know for what is IC-Compiler(from synopsys) not ISE (my mistake) , but is good to know.
So now I'm using(where I'm studying) Icarus verilog (it's a free verilog compiler + GtkWave for displaying simulation waves, Icarus Verilog can synthesize verilog to gate level, I belive it's EDIF format.) But I do not know any tool which can read that format(I mean, to display schematic,of the gate level) . I will ask at my University what tools they have for study purpose.
So I have one more question, synopsys IC compiler, saber, primetime, cosmosscope what is for?
And I've understood that I need some technology file for synthesis(I want to learn to see how it will be synthesized my verilog code, and after that time constraints, just for study).
Is there any technology files free(for study purpose). And where can I download them?
Thanks in advance, and I WISH YOU A HAVE A GOOD DAY !
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viju
Joined: 26 Nov 2006
Posts: 52
Helped: 8
Location: Bangalore
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| 06 Oct 2008 16:41 New in Digital design and synthesis...some questions I have. |
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Hi,
EDIF file is supported by many tools. For exmple OrCad schematic capture(schematic and PCB designing software) is capable to open this files. EDIF is very comman standard across industry.
I don't know about the tools like "saber" and "cosmosscope "... I know about primetime. Primeime is Static timing ananlysis(STA) tool from synopsys. It is worlds most recognized eda tool for STA. It is infact sign-off tool for sta.
For the technology library.. you may find it on some university sites... like Oklahoma State University.
visit : http://avatar.ecen.okstate.edu/projects/scells/
to download.
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salma ali bakr
Joined: 27 Jan 2006
Posts: 943
Helped: 79
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| 31 Oct 2008 10:45 Re: New in Digital design and synthesis...some questions I h |
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| dexter_ex_2ks wrote: |
Is there any technology files free(for study purpose). And where can I download them?
Thanks in advance, and I WISH YOU A HAVE A GOOD DAY ! |
There's MOSIS, they support academic institutions...
www.mosis.com
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santhosh007
Joined: 27 Aug 2008
Posts: 51
Helped: 13
Location: Bangalore
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| 31 Oct 2008 12:15 Re: New in Digital design and synthesis...some questions I h |
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| dexter_ex_2ks wrote: |
Thank you very much, for your answer.
So ISE is from Xilinx, I understood. Actually a wanted to know for what is IC-Compiler(from synopsys) not ISE (my mistake) , but is good to know.
So now I'm using(where I'm studying) Icarus verilog (it's a free verilog compiler + GtkWave for displaying simulation waves, Icarus Verilog can synthesize verilog to gate level, I belive it's EDIF format.) But I do not know any tool which can read that format(I mean, to display schematic,of the gate level) . I will ask at my University what tools they have for study purpose.
So I have one more question, synopsys IC compiler, saber, primetime, cosmosscope what is for?
And I've understood that I need some technology file for synthesis(I want to learn to see how it will be synthesized my verilog code, and after that time constraints, just for study).
Is there any technology files free(for study purpose). And where can I download them?
Thanks in advance, and I WISH YOU A HAVE A GOOD DAY ! |
cosmoscope is waveform viewer.. you can view fsdb,vcd files....
IC compiler from synopsys used for physical implementation
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