savour
Joined: 07 Sep 2008
Posts: 11
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 04 Oct 2008 15:44 Is block Vhdl statement Synthesizable? |
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I want to use the "block" vhdl statement for structural modularity.
From your experience with synthesizers (design compiler, sinplify, qu(at)rtus, xilinx ise) is that a valid vhdl statement for synthesis?
Also can "block" statement easily converted to verilog with the vhdl to verilog conversion tools?
Many thanks,
savour
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