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hawks4peace
Joined: 06 Apr 2006
Posts: 15
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 04 Oct 2008 5:46 question reg RTL coding |
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Hello
Can any one tell me what is the difference between Register Transfer Level (RTL) style coding and normal HDL coding. I mean is there any difference at all or is it just a structural coding of logic diagram (combinatorial cloud and register pairs).
Thank you for your help
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madhavisai
Joined: 03 Feb 2008
Posts: 35
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| 07 Oct 2008 17:15 question reg RTL coding |
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| In RTL we assume that the code we r writing which is a vector quantity which will transfer betweenfunctional units.
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hawks4peace
Joined: 06 Apr 2006
Posts: 15
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| 07 Oct 2008 17:45 Re: question reg RTL coding |
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Thanks for the reply.
I couldn't understnd the concept properly.
Can you please explain it in more detail or if u know a source or website can you please guide me to it.
regards
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ramana459
Joined: 01 Apr 2008
Posts: 20
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| 08 Oct 2008 19:25 Re: question reg RTL coding |
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When you written the code in verilog or vhdl (called HDL coding) in Xilinx or @ltera plotform, after synhesis it will give one netlist file. The main of aim of this netlist is to fix into FPGA or DE2board,
If you synthesis this verilog or vhdl code in RTL Compiler(RC from Cadence, using different library files which was given by foundries) you will get netlist file. This netlist useful for particular foundry only(which library file you used).
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ljxpjpjljx
Joined: 05 May 2008
Posts: 198
Helped: 4
Location: Shang Hai
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| 09 Oct 2008 3:39 Re: question reg RTL coding |
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| you should obey the coding style in RTL level, not the gate level!
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kevine
Joined: 03 Jul 2006
Posts: 8
Helped: 1
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| 09 Oct 2008 6:16 question reg RTL coding |
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you must use RTL style code if the design needs synthsis and transfer to netlist ;
you can use behavior level style code when your target is function model ,that you will use behavior style conveniently and freely. only your code is compatible for HDL syntax, this style maybe the normal style you said above
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