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Beardolphinaries
Joined: 21 Aug 2007
Posts: 39
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 03 Oct 2008 16:03 VHDL? Verilog? Verilog-A? Verilog-AMS? |
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Hi, could anyone tell what's the difference among
VHDL, Verilog, Verilog-A and Verilog-AMS please?
Thanks a lot.
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mpig09
Joined: 26 Aug 2005
Posts: 123
Helped: 6
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| 04 Oct 2008 14:34 Re: VHDL? Verilog? Verilog-A? Verilog-AMS? |
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Dear Beardolphinaries :
I think:
VHDL / Verilog: for digital design and mixed mode simulate
verilog-A : for analog designer, not good idea for mixed mode mode simulate
mpig
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Beardolphinaries
Joined: 21 Aug 2007
Posts: 39
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| 08 Oct 2008 12:59 Re: VHDL? Verilog? Verilog-A? Verilog-AMS? |
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| Thank very much.
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olzanin
Joined: 01 Sep 2003
Posts: 30
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| 08 Oct 2008 14:45 Re: VHDL? Verilog? Verilog-A? Verilog-AMS? |
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Hello,
VHDL and Verilog are competitors and both are for digital design.
With Verilog-A you can program in your analog design some ideal digital cells.
Verilog-AMS is for mixed simulations.
olzanin
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sparso
Joined: 30 Dec 2006
Posts: 63
Helped: 1
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| 17 Oct 2008 2:57 VHDL? Verilog? Verilog-A? Verilog-AMS? |
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I use verilog for purely digital stuff.
VHDL is used mainly in Europe and Japan.
Not much in the US. Verilog-A to model analog stuff
when I need speedy sim time. Have not used Verilog-AMS yet but I think Verilog A is a subset of AMS.
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