viju
Joined: 26 Nov 2006
Posts: 52
Helped: 8
Location: Bangalore
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 03 Oct 2008 15:55 PLL lock , clocking and SoC (system) level understanding |
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Hi All,
I have a question on clking scheme in a SoC. Say there is a PLL in SoC. So clk supplied to all the modules from PLL. Now PLL needs to be locked before it gives accurate clk freq and expected duty cycle. This means that we should not suppy the unstable clk(i.e. clk before PLL lock is achieved).
Main question... So how this is implemented in SoC ?
I can think of following scenarios...
1.Does all the modules will be reset state till PLL lock is achived ?
2.Or our system reset pulse will be so long that it will be released only when the PLL lock is achived ?
3. Or system reset will pulse will be of normal duration, but the this pusle will be streached internally to SoC till PLL lock is achived ?
4. If any of above scheme is implemented... what about the all other chips on system(i.e. on the board)? How would other chips come to know that our SoC is came out of reset and we can start transfer /interaction with it? Does our SoC provide any flag/signal/bit to indiacate that it is ready for the operation?
Please let me know your views/ methods to implement above scenario.
Please let me know if I am missing any thing compared to standard Industrial Pratice...
Thanks you in advance...
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