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please help, Design compiler problem

 
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elec-eng



Joined: 16 Nov 2006
Posts: 236
Helped: 14


Post02 Oct 2008 17:57   please help, Design compiler problem

hi all

I have a problem reading a file into Design compiler 2001

when I write the following command in the design analyzer command window

Code:
read -format vhdl {“./vhdl/synopsys.vhd”}


the following error occures




my .synopsys_dc.setup file is ok
I coppied it from the DC tutorial to my work directory
so it is not a setup file problem

and the gui file>read generates an internal system error "it is a known bug in the design analyzer gui not an error with my installation"

please help me guys

thanks
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santumevce1412



Joined: 08 Jan 2008
Posts: 24


Post03 Oct 2008 10:07   Re: please help, Design compiler problem

Pls chek the path once.....
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naveen_zs



Joined: 10 Nov 2008
Posts: 16
Helped: 1


Post11 Nov 2008 5:54   Re: please help, Design compiler problem

Hi
There will be two reasons to get these type of errors

1. The path mentioned will be wrong
2. You might me using db (which was generated with later version ) when compared to version you are using for synthesis
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nine8



Joined: 18 Sep 2007
Posts: 36
Helped: 1


Post14 Nov 2008 7:54   please help, Design compiler problem

are you sure VHDL format file can be loaded into design by "read -format vhdl" command ?
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salma ali bakr



Joined: 27 Jan 2006
Posts: 943
Helped: 79


Post14 Nov 2008 15:54   Re: please help, Design compiler problem

where did you specify your libraries ?!!
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vlsichipdesigner



Joined: 09 May 2007
Posts: 84
Helped: 4


Post15 Nov 2008 13:48   Re: please help, Design compiler problem

hi,

my 2 cents,

* source your .synopsy-dc.setup file which has the path (search path, link and target libraries specified)
* try to change the version to the latest if available.
* Dont use the absolute path, give the full path to read in the file
* In case if the RTL calles libraries, check whether you have the DCOBj created in the same version of which your are using to readin the RTL
* check reading the RTL with "analyze" command.

happy designing
chip design made easy
http://www.vlsichipdesign.com
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