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santumevce1412
Joined: 08 Jan 2008
Posts: 24
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 02 Oct 2008 6:24 frequency divider |
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Design a state machine to divide the clock by 3/2.
I/p frequency - 50MHz
o/p requency - 33.3MHz
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nisarg001
Joined: 26 Sep 2007
Posts: 9
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| 02 Oct 2008 9:07 frequency divider |
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| If your output frequency is fixed at 33.3 MHz then you may simply use the oscillator working at that freq.
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wudanyu
Joined: 02 Oct 2008
Posts: 4
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| 02 Oct 2008 14:14 Re: frequency divider |
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you can design an 2-bit counter named "cnt[1:0]", return "00" when count to "10", negedge of clk;
then you can generate an 2/3 clk by this statement:
assign clk_out=clk&~cnt[1];
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ranjithp
Joined: 02 Mar 2008
Posts: 2
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| 03 Oct 2008 12:46 Re: frequency divider |
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| what about the duty cycle??
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ramana459
Joined: 01 Apr 2008
Posts: 20
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| 08 Oct 2008 20:26 Re: frequency divider |
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use this url
http://asic-world.com/examples/verilog/divide_by_45.html#Divide_By_4.5_Counter
by using this code you modify your code into according your interest
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