| Author |
Message |
santumevce1412
Joined: 08 Jan 2008
Posts: 24
|
 02 Oct 2008 6:22 4-t0-1 mux in verilog |
|
|
|
A 4-to-1 mux using if-else and case is given
if-else statements
if(sel_1 == 0 && sel_0 == 0) output = I0;
else if(sel_1 == 0 && sel_0 == 1) output = I1;
else if(sel_1 == 1 && sel_0 == 0) output = I2;
else if(sel_1 == 1 && sel_0 == 1) output = I3;
Using case statement
case ({sel_1, sel_0})
00 : output = I0;
01 : output = I1;
10 : output = I2;
11 : output = I3;
default : output = I0;
endcase
# What are the advantages / disadvantages of each coding style shown above?
# How Synthesis tool will give result for above codes?
# What happens if default statement is removed in case statement?
# What happens if combination 11 and default statement is removed? (Hint Latch inference)
pls answer these questions..............
|
|
| Back to top |
|
 |
viju
Joined: 26 Nov 2006
Posts: 52
Helped: 8
Location: Bangalore
|
| 02 Oct 2008 15:51 4-t0-1 mux in verilog |
|
|
|
Hi ,
For the coding with if-else, synthesis tool will implement the priority based MUX logic. So it will have a more delay as priority chain is created.
For the coding with case statemetn, it will create a parallel MUX structure, so delay will be less.
As so far as synthesis tool result, above text already answer this.
Regarding the removal of default statement in case statement....In this case you have mentioned all the four possible conditions so it is full case and hence no need to write default statement... so even if you remove it wont effect your hardware
Regarding the combination "11" and defalut statement removal, in case statement... Latch will be infered... as you have already mentioned as a hint... latch will be infered, becasue synthesis tool don't have idea, what to do when case item become s"11".. so it will try to keep the previous value in the output.... so it will infere the latch like logic in order to produce the previous output in case of "11" in case item.
Hope this helps...
let us know if you have any other specific doubts......
|
|
| Back to top |
|
|
FvM
Joined: 22 Jan 2008
Posts: 2635
Helped: 431
Location: Bochum, Germany
|
| 02 Oct 2008 22:13 4-t0-1 mux in verilog |
|
|
|
| As both code implementations are logically equivalent, you can't know a priory that they are treated different by a synthesis tool. It may be the case with a particular tool (do you know of any for sure?), but an identical result for both constructs is much more likely, I think.
|
|
| Back to top |
|
|
vlsichipdesigner
Joined: 09 May 2007
Posts: 84
Helped: 4
|
| 12 Oct 2008 13:18 Re: 4-t0-1 mux in verilog |
|
|
|
my 2 cents,
I agree with viju and i agree with FvM
As most of the articles in the internet based on verilog coding styles towards are inclined to the synthesis tool (synopsys design compiler). This is the reason for viju answer i believe.
But for the rtl quoted i believe , the design compiler will infer a priority encoder for ifelse and a mux for the case statement.
For mux situation the tool understanding we can agree both the RTL constructs are logically correct but for the priority encoder the first RTL will be the right choice.
I believe we can use tool pragmas to get things done for example //infer_mux for the first RTL ??
hope i made sense
happy designing
best regards,
chip design made easy,
http://www.vlsichipdesign.com
|
|
| Back to top |
|
|
