surisingh
Joined: 14 Jun 2007
Posts: 23
Helped: 1
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 01 Oct 2008 21:41 VHDL to Verilog doubt |
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Hi,
I am converting a VHDL code into verilog. I have a procedure in VHDL. The input argument passed to this procedure has different width at different time. Say for example some time I pass 8 bit vector and some time I may pass 16 bit vector.
Inside the procedure they are using 'left and 'right for manipulation.
I know task is equivalent to procedure. But we can't pass an argument with variable width. Isn't it? How to overcome this problem in verilog?
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