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savour
Joined: 07 Sep 2008
Posts: 11
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 30 Sep 2008 21:52 Re: Multioperand addition in VHDL ? |
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Lets suppose q0,p0, p1,q1 are 8 bit unsigned vectors.
I want to calculate the expression :
delta = ((p0-q0)<<2 + (p1-q1) + 4)>>3
The expression can take values between [-158,159] ,
so delta needs to be 9 bit length including sign in 2'complement.
It is possible to describe it in VHDL as multioperand addition without
separately implementing each addition ?
Added after 37 minutes:
And another question about multioperand addition.
Lets have the a,b,c,d unsigned 8 bit vectors and the following expression
result = a+b+c+d , the result has to be 10 bits long.
Is the following expression correct in vhdl?
result <= "00"&a +"00"&b +"00"&c +"00"&d;
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FvM
Joined: 22 Jan 2008
Posts: 2635
Helped: 431
Location: Bochum, Germany
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| 01 Oct 2008 10:38 Re: Multioperand addition in VHDL ? |
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| The expression is incorrect, cause & don't has a precendence over +. Needs parantheses.
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savour
Joined: 07 Sep 2008
Posts: 11
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| 02 Oct 2008 0:15 Re: Multioperand addition in VHDL ? |
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You are absolutely right FvM, i forgot them.
The correct one is:
result <= ("00"&a) +("00"&b) +("00"&c) +("00"&d);
Lets say for example that a 9 bits, b 8 bits ,c 7 bits and d 7 bits are unsigned and we add them in the following expression :
result = a + b+ c +d.
The maximum value of the expression above is 1020, so result has to be 10 bits long.
The VHDL expression will be :
result <= ('0'&a) + b + c +d;
Will this expression produce the correct synthesis results?
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FvM
Joined: 22 Jan 2008
Posts: 2635
Helped: 431
Location: Bochum, Germany
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| 02 Oct 2008 8:03 Multioperand addition in VHDL ? |
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| Yes.
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megastar007
Joined: 20 Feb 2007
Posts: 82
Helped: 5
Location: Munich
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| 02 Oct 2008 10:37 Re: Multioperand addition in VHDL ? |
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| y cant u use unsigned extension to bitwidth of result
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