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rk29
Joined: 30 Sep 2008
Posts: 3
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 30 Sep 2008 7:47 Mixed(verilog & VHDL) top and bottom examples |
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Hi All,
Where I can get the simple examples of Mixed(verilog & VHDL) top and bottom examples.
Thanks in advance
rk
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viju
Joined: 26 Nov 2006
Posts: 52
Helped: 8
Location: Bangalore
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| 30 Sep 2008 15:09 Mixed(verilog & VHDL) top and bottom examples |
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| which tool you are using for simulation? I think VCS -MX will have some examples on how to compile Mixed language design.
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rk29
Joined: 30 Sep 2008
Posts: 3
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| 02 Oct 2008 2:43 Re: Mixed(verilog & VHDL) top and bottom examples |
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Hi viju,
I am using NCSIM.
Thanks
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