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surisingh
Joined: 14 Jun 2007
Posts: 23
Helped: 1
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 29 Sep 2008 19:09 real to vec in VHDL |
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Hi,
Can anyone tell me how to convert a real value (b/w +1.0 and -1.0) in VHDL into std_logic_vector(13 downto 0) and again revert back this std_logic_vector into real value.
I tried to write a function to convert these things,but it didn't work out for me.
Take an example of -0.000136114. I want to convert this real value into 14 bit vector and again convert this vector into real so that i have to get the final real value which should be equal to -0.000136114.
Suresh
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FvM
Joined: 22 Jan 2008
Posts: 2635
Helped: 431
Location: Bochum, Germany
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| 29 Sep 2008 19:20 Re: real to vec in VHDL |
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It can be done in simulation and as compile time operation for synthesis.
| Code: |
slv_val <= STD_LOGIC_VECTOR(CONV_SIGNED(INTEGER(r_val*8192.0),14));
r_val <= REAL(CONV_INTEGER(SIGNED(slv_val)))/8192.0; |
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surisingh
Joined: 14 Jun 2007
Posts: 23
Helped: 1
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| 29 Sep 2008 21:28 Re: real to vec in VHDL |
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| Thanks.. But I tried with functions in VHDL. I got the same result in both my functions as well as the one you suggested. That is if i give -0.000136114 to real_to_vec then i am getting 14'h3FFF and if I give this value to vec_to_real, i am not getting -0.000136114, instead I am getting -0.00012207. Is it the expected one?
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vomit
Joined: 14 Jun 2002
Posts: 144
Helped: 10
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| 29 Sep 2008 23:34 Re: real to vec in VHDL |
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0,00012207 is 1/8192, the finest precision you can represent in 13 bit. As you first multiply by 8192, then round to the nearest integer, and then divide again, you get a roundoff error of 1 least significan bit, or 1/8192.
In other words: the result is as precise as it can get. Your starting value is -0.000136114, which is -1.115/8192. You round to -1/8192 by going from real to the fixed point integer representation. What else could one expect?
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surisingh
Joined: 14 Jun 2007
Posts: 23
Helped: 1
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| 30 Sep 2008 23:24 Re: real to vec in VHDL |
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Thank you guys. I understand..
Regards,
CSuresh
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