electronics forum

Rules | Recent posts | topic RSS | Search | Register  | Log in

Seed in system verilog


Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Seed in system verilog
Author Message
pkamboj_11



Joined: 04 Jan 2008
Posts: 2


Post05 Sep 2008 7:37   

Seed in system verilog


I am writing a random test with seed variable in system verilog.I want to run the same test with different seed so i want my sequence to be nondeterministic by seeding the $urandom function with an extrinsic random variable, such as the time of day. How can i know time of day in stytem verilog.
Back to top
Google
AdSense
Google Adsense




Post05 Sep 2008 7:37   

Ads




Back to top
jbeniston



Joined: 05 May 2005
Posts: 193
Helped: 25


Post05 Sep 2008 11:02   

Seed in system verilog


Good question. I don't know of one.

Perhaps you can generate the seed with a shell script, save it to a file, then read it in using $fread. Alternatively you could create your own PLI library that implements it.

Strange ommision if it doesn't exist.
Back to top
Arabic versionBulgarian versionCatalan versionCzech versionDanish versionGerman versionGreek versionEnglish versionSpanish versionFinnish versionFrench versionHindi versionCroatian versionIndonesian versionItalian versionHebrew versionJapanese versionKorean versionLithuanian versionLatvian versionDutch versionNorwegian versionPolish versionPortuguese versionRomanian versionRussian versionSlovak versionSlovenian versionSerbian versionSwedish versionTagalog versionUkrainian versionVietnamese versionChinese version
Post new topic  Reply to topic    EDAboard.com Forum Index -> ASIC Design Methodologies & Tools (Digital) -> Seed in system verilog
Page 1 of 1 All times are GMT + 1 Hour
Similar topics:
System Verilog Random Seed Variation (4)
How to see Seed Value in System Verilog (2)
System Verilog and System Verilog Assertions Tutorial (1)
Comparison of VHDL, Verilog, and System verilog (2)
Advantage of System C over System Verilog (2)
system verilog & verilog (2)
System C, System verilog, or Vera (11)
System C & system Verilog (9)
copper seed (5)
seed value (2)


Abuse || Administrator || Moderators || Support us || sitemap
topic RSS