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among
Joined: 26 Jul 2008
Posts: 33
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 30 Aug 2008 12:17 clock and data rate |
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hi
any one tell me the minimum required clock frequency for the 1 gbps data rate
thank you
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rjainv
Joined: 18 Feb 2007
Posts: 147
Helped: 14
Location: Bangalore, India
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| 30 Aug 2008 15:18 clock and data rate |
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| what is your bus width ? Divide 1gpbs with your bus width, that would give you the minimum clock frequency you need.
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FvM
Joined: 22 Jan 2008
Posts: 2625
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Location: Bochum, Germany
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| 30 Aug 2008 20:24 Re: clock and data rate |
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| That's the word rate or maximum (for unequivocal frame synchronisation) rather than the minimum clock frequency. An integer part of the word rate can be used as clock frequency as well.
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rjainv
Joined: 18 Feb 2007
Posts: 147
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Location: Bangalore, India
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| 31 Aug 2008 8:56 Re: clock and data rate |
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| FvM wrote: |
| That's the word rate or maximum (for unequivocal frame synchronisation) rather than the minimum clock frequency. An integer part of the word rate can be used as clock frequency as well. |
Can you give some more background on "unequivocal frame synchronisation" ?
I think any integer part of word rate needs to be rouned-off to next higher integer ( ceiling), hence would be higher than what I said.
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FvM
Joined: 22 Jan 2008
Posts: 2625
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Location: Bochum, Germany
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| 31 Aug 2008 10:48 Re: clock and data rate |
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| As an example with a 125 MHz word rate, 1000 MHz bit rate serial transmission: An unequivocal frame clock could be 125 Mhz, but also 62.5 or e. g. 25 MHz. If you use serializer/deserializer IP from an FPGA compiler tool as @ltera qu(at)rtus Megafunction, it will allow you a respective selection.
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rjainv
Joined: 18 Feb 2007
Posts: 147
Helped: 14
Location: Bangalore, India
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| 31 Aug 2008 11:00 clock and data rate |
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I am still missing your point.
If we move from 125 Mhz to 25 Mhz, then we definitely need to increase bus width from 8 bits to 40Bits to match the bandwidth.
At any point whether its before serializer/deserializer or after it, the bus width should be such that it gives bandwidth greater than 1Gbps at given frequency of clock at that point.
So if FPGA compiler tool gives option of 25 Mhz, guessing that this 25Mhz clock is for write side of serializer, it would increase the size/width of frame accordingly ( I am assuming you are referrring the input to serializer as a frame)
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