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Vertex 4 digital I/O usage for high frequency signals

 
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saikat



Joined: 21 Oct 2005
Posts: 46
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Location: mumbai
Post28 Aug 2008 8:01   Vertex 4 digital I/O usage for high frequency signals
What is the maximum possible frequency of a signal that can be properly handled by Vertex 4 digital I/O pin as an input?

I need to sample high frequency signal in Vertex 4 and wondering about the maximum frequency handling capacity of the digital I/O of the device.
The datasheet does not clearly mention this.Crying or Very sad
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saikat



Joined: 21 Oct 2005
Posts: 46
Helped: 4
Location: mumbai
Post01 Sep 2008 11:52   Re: Vertex 4 digital I/O usage for high frequency signals
OK, I like to ask the question in a different way with an example.



Lets say, there is an external 64 bit bus (LVTTL) whose maximum frequency is 100MHz and it is connected to 64 digital I/O pins of Vertex 4. I need to sample the bus at every 2ns (i.e. @ 500MHz clock), and want to dump the sampled values into an internal FIFO at the same speed of 2ns (i.e. @ 500MHz clock).



Now tell me whether this arrangement will be implementable in Vertex 4? Or can I drive my design @ 500MHz in Vertex 4?
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