avimit
Joined: 16 Nov 2005
Posts: 415
Helped: 68
Location: Fleet, UK
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 28 Aug 2008 9:51 Re: VHDL enquirey |
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VHDL does NOT provide a method by which you can access signals down in hierarchy at top level or at any other level. However there are ways to do so
1). Declare signals in a package instead of in a entity/architecture. Then compile this package, and make it visible in modules deep inside the hierarchy and in the modules you would like to access the same signal, say in test bench. Then you can access the signal at both places
2). If you are using modelsim, you can use something called 'signal spy' Which will make your signals visible at anylevel, no matter how deep in hierarchy they are.
Example:
| Code: |
| init_signal_spy("/top/uut/inst1/sig1","/top/top_sig1",1,1); |
Hope it hepls
Kr,
Avi
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