anoop12
Joined: 29 Nov 2006
Posts: 67
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 27 Aug 2008 15:04 Round robin fashion VHDL |
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Hi
There are four inputs say i1,i2,i3,i4. And corrosponding four outputs
o1,o2,o3,o4. I have to assign I to O in round robin fashion.
e.g. if i3 is true then it is routed to o3 else i4 is checked for true
and then i1 and at lase i2.This process continues. There should not be
any priority.
I need a general VHDL description for this. Can anyone do it?
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mmarco76
Joined: 04 Jan 2008
Posts: 85
Helped: 6
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| 27 Aug 2008 15:50 Round robin fashion VHDL |
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you need to use an if or a case with all the statements that describe exactly what to do also if more of them are at 1.
example.
if (i1='1') and (i2='0') and (i3='0') and (i4='0') then
signal_out <= out1;
elsif (i1='0') and (i2='1') and (i3='0') and (i4='0') then
signal_out <= out2;
elsif (i1='0') and (i2='0') and (i3='1') and (i4='0') then
signal_out <= out3;
elsif (i1='0') and (i2='0') and (i3='0') and (i4='1') then
signal_out <= out4;
else -- see note
signal_out <= out1;
end if;
note: in the else you need to define what to do if more than 1 input is at 1? and what if all are at zero?
you need to know what you wanna do in all that case also if they shall never happen.
if you're sure they'll never happen you could simply put out signal equal to one of your signals. in that case you can put your out equal to 1 as I've written.
Added after 10 minutes:
I forgot but all this is true if it's under a clock (all design in FPGA shall be synchronous in order to work reliably)
Else you cannot use the "if" clause, but need the with select construct.
example:
sel(3 downto 0) <= in4 & in3 & in2 & in1;
with sel select
signal_out <= out1 when b"0001",
<= out2 when b"0010",
<= out3 when b"0100",
<= out4 when b"0100",
<= out1 when others; -- valgono sempre le considerazioni di cui sopra in cui devi specificare cosa fare in TUTTE le condizioni.
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