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citizen
Joined: 14 May 2008
Posts: 112
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 27 Aug 2008 11:53 on alterastratix 2 can we do this |
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hi
im using @ltera stratix 2 fpga which is having 4 enhanced plls and 8 faster plls.
can i by using this fpga can i generate 980 Msps clock by using 2 mhz reference clock
(sorry may any technical terms may be wrong because im new to fpga coding and i have to design dqpsk modulator to get if of 240 mhz at output at the dac,any one clarify my doubt and help me )
thank you
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mmarco76
Joined: 04 Jan 2008
Posts: 85
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| 27 Aug 2008 15:26 on alterastratix 2 can we do this |
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If your input clock is only 2 MHz I think you'll have some throuble in make it as input in PLL.
All PLL have a bandwith beyond the limit of it they don't work.
I'm not user of the one of Stratix 2 (you should check on @ltera web site) but usually it's nothing under 16MHz.
Moreover you shall consider to input a FPGA with faster CLK expecially if you need to raise your frequency so high.
Moreover 980Msps = 980 Mega Sample per Second, but i think you mean something different.
I mean 1Msps = 10^6 each 1MHz clk.
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FvM
Joined: 22 Jan 2008
Posts: 2632
Helped: 431
Location: Bochum, Germany
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| 27 Aug 2008 20:22 Re: on alterastratix 2 can we do this |
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| Stratic II PLL supports input clock down to 2 MHz. 980 MHz VCO frequency would be available only with fastest speed grade, but the regular logic core can't work at that frequency. There are howver other techniques as combining phase shifted clocks, using dual-edge registers or dedicated serializer hardware. 240 MHz DQPSK should be possible anyway.
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