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Mehdi1357
Joined: 18 Jan 2008
Posts: 25
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Location: the Earth
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 26 Aug 2008 8:17 vhdl dual edge |
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Hi everbody
How can write a process in VHDL for dual edge counter(counter increases its value each time a rising or falling edge occurs)?
thanks
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avimit
Joined: 16 Nov 2005
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Location: Fleet, UK
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26 Aug 2008 9:59 vhdl rising edge |
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You will have to have 2 counters, one which work on -ive edge, and the other which work on +ive edge. Each counter will increment the count by 2. One will start with 0 the other will start with 1. You can then multiplx the o/p value as desired.
kr,
Avi
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Mehdi1357
Joined: 18 Jan 2008
Posts: 25
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Location: the Earth
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27 Aug 2008 13:33 vhdl double edge |
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Hi
I appreciate your answer.is there a more simple solution for processing of both edges of a input signal in a PROCESS block.please write VHDL code.
best regards.
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avimit
Joined: 16 Nov 2005
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Helped: 69
Location: Fleet, UK
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27 Aug 2008 14:33 edgecounter |
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No there is no simpler answer or a method to do this in a single procedural code, which will be synthesizeable
Kr,
Avi
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FvM
Joined: 22 Jan 2008
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Location: Bochum, Germany
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mmarco76
Joined: 04 Jan 2008
Posts: 85
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27 Aug 2008 15:21 vhdl edge |
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Your question is very simple.
If the signal you wanna count is a clock simply your code will be something like this:
process(reset, clk).
begin
if reset = '1' then
counter <= (others =>'0');
elsif clk'event then
counter <= counter +1;
end if;
end process;
If you wanna count a signal that is not a clock, but it's clocked by your clock under certain condition (signal last at least 3 clk before changing state) you can detect the 2 front and then increase your counter by them.
Hoping to help you with this simple answer.
If need more help ask with more details.
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lucbra
Joined: 30 Oct 2003
Posts: 160
Helped: 6
Location: Belgium
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05 Sep 2008 15:22 vhdl rising and falling clock edge |
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| Yes but this code is NOT synthesisable. There is no hardware FF that supports this.
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karikalan_t79
Joined: 20 Oct 2008
Posts: 99
Helped: 1
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22 Oct 2008 5:27 dual edge counter |
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| tool will tell this is impoosible to attend a ff in the design and result in error
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Mehdi1357
Joined: 18 Jan 2008
Posts: 25
Helped: 1
Location: the Earth
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22 Oct 2008 11:12 edge counter vhdl |
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| mmarco76 wrote: |
Your question is very simple.
If the signal you wanna count is a clock simply your code will be something like this:
process(reset, clk).
begin
if reset = '1' then
counter <= (others =>'0');
elsif clk'event then
counter <= counter +1;
end if;
end process;
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I appreciate you for your answer , but your code isn't synthesizeble in ISE version 10.1 (related to Xilinx's productions).
this problem will solve by using two processes , one for rising edge and another for falling edge then we must mix these results together.
best regards.
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22 Oct 2008 11:12 Ads |
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Core1
Joined: 17 Oct 2008
Posts: 1
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22 Dec 2008 23:12 vhdl edge counter |
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| Mehdi1357 wrote: |
Hi everbody
How can write a process in VHDL for dual edge counter(counter increases its value each time a rising or falling edge occurs)?
thanks |
it's not the synthesizer, it's the target
look at this simple code: (sorry, I'm a verilog guy)
always @(posedge clk or negedge clk)
x = x + 1;
It is synthesizable and it does work in some CPLD's like XC2Sxx (Xilinx)
The target you point the synthesizer to must have dual-edge support.
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Nir Dahan
Joined: 19 May 2008
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Location: Munich, Germany
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