| Author |
Message |
ASIC_intl
Joined: 18 Jan 2008
Posts: 199
|
 26 Aug 2008 6:39 designing divide by 3/2 counter |
|
|
|
| How to design a divide by 3/2 counter which is synthesizable?
|
|
| Back to top |
|
 |
natg9
Joined: 17 Jul 2008
Posts: 37
Helped: 7
|
| 26 Aug 2008 7:17 Re: designing divide by counter |
|
|
|
Hi pal
i have a doc regarding the same
but due to some reason i m getting this error msg from EDABOARD
Sorry but this file has already been posted! Better copy and paste following link into your post, where the same file is located:
http://www.edaboard.com/viewtopic.php?p=280661#280661
so give me ur email id i ll post it to u
regards
natg
|
|
| Back to top |
|
|
AdvaRes
Joined: 14 Feb 2008
Posts: 623
Helped: 33
|
| 26 Aug 2008 7:51 designing divide by 3/2 counter |
|
|
|
Hi,
Yeah use the document Clock_Dividers_Made_Easy.pdf, it is very usefull. You can make easily 1/2,3/2 and 1/5 divider with 50% duty cycle
|
|
| Back to top |
|
|
ASIC_intl
Joined: 18 Jan 2008
Posts: 199
|
| 26 Aug 2008 8:01 Re: designing divide by 3/2 counter |
|
|
|
Can u make a divide by 3/2 counter with using of two FSMs among them one operates in positive edge and the other at negative edge.
The clock_divider_made_easy.pdf approach is different.
|
|
| Back to top |
|
|
speedforu
Joined: 23 Oct 2007
Posts: 4
|
| 27 Aug 2008 11:08 designing divide by 3/2 counter |
|
|
|
lep is the pulse you generate whenever you FSM counter counting clock edges becomes 0. lep_d1 is the output of the register with input lep clocked on negative edge. The output is a simple OR of these 2 signals.
|
|
| Back to top |
|
|
ASIC_intl
Joined: 18 Jan 2008
Posts: 199
|
| 28 Aug 2008 6:54 Re: designing divide by 3/2 counter |
|
|
|
| we want a divide by 3/ 2 counter not a divide by 3 counter whose timing diagram has been drawn.
|
|
| Back to top |
|
|
dcreddy1980
Joined: 03 Dec 2004
Posts: 128
Helped: 8
Location: Munich, Germany
|
| 28 Aug 2008 10:07 designing divide by 3/2 counter |
|
|
|
| Hi ASIC_intl, Can you give me a reason why do u want to go for FSM approach for the divide by 3/2 clock generation?
|
|
| Back to top |
|
|
ASIC_intl
Joined: 18 Jan 2008
Posts: 199
|
| 29 Aug 2008 3:52 Re: designing divide by 3/2 counter |
|
|
|
There is no reason particularly. It can be done in that way also. The way suggested by the document of STMicroelectronics is a traditional approach.
Can u solve in the way I stated!
|
|
| Back to top |
|
|
Peter Chang
Joined: 05 Oct 2006
Posts: 8
Helped: 1
Location: TAIWAN
|
| 29 Aug 2008 6:25 Re: designing divide by 3/2 counter |
|
|
|
I think it needs a PLL.
Peter
|
|
| Back to top |
|
|
