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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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 25 Aug 2008 9:45 feature sixe for FPGA |
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| What is the Feature size for FPGA design? We can say 135 nm or 90 nm design in ASIC? How can I represent the same in FPGA?
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jbeniston
Joined: 05 May 2005
Posts: 85
Helped: 8
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| 26 Aug 2008 18:22 feature sixe for FPGA |
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| Exactly the same way (FPGAs are ASICs). Virtex 5 parts are 65nm. Virtex 4 parts are 90nm.
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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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| 28 Aug 2008 6:58 Re: feature sixe for FPGA |
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| The combinational logic is realized by using LUTs not by CMOSes or NOSes as in ASIC gates? How can u then define feature sizes for LUTs?
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ASIC_intl
Joined: 18 Jan 2008
Posts: 199
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| 29 Aug 2008 3:54 Re: feature sixe for FPGA |
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| The combinational logic is realized by using LUTs not by CMOS or MOS as in ASIC gates? How can u then define feature sizes for LUTs?
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