SVA assertions question

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sree205

Joined: 13 Mar 2006
Posts: 421
Helped: 30

25 Aug 2008 7:59 passing a parameter to an sva assertions

Hi all,
I'm trying to come up with an assertion using systemverilog with a small difference. a typical property is,

property p_tcnst;
@(posedge clk)
$fell (variable_name) |->
##tcnst $rose (variable_name);
end property

In this property, would it be possible to substitute the tcnst parameter with a RTL variable?

ankurgupta74

Joined: 25 Aug 2008
Posts: 3

26 Aug 2008 7:06 Re: SVA assertions question

no. it is a constant.

boardlanguage

Joined: 06 Apr 2007
Posts: 96
Helped: 4

26 Aug 2008 16:17 Re: SVA assertions question

Code:

property p_tcnst;
@(posedge clk)
$fell (variable_name) |->
##[b]tcnst[/b] $rose (variable_name);
end property

You may already know this, but but tcnst can be a declared parameter or other compile-time constant. (it doesn't have to be a literal constant.)

Code:

parameter int blah_start = 94;
parameter int blah_end = 121;

// tcnst = (#cycles) pulse-width between $fell and $rose
parameter int tcnst = blah_end - blah_start;

sree205

Joined: 13 Mar 2006
Posts: 421
Helped: 30

27 Aug 2008 7:39 SVA assertions question

The problem is, even if tcnst is a parameter, i won't be able to change it at run time. i'm not able to change the tcnst value based on some RTL signal value.