vinodkumar
Joined: 05 Oct 2006
Posts: 229
Helped: 10
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 24 Aug 2008 12:22 basic doubt clock in fpga |
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1)I found the Gclk pins of 8 in FPGA Spartan3,does it mean that we need to assign clock pins only to those.
2)Does there any order of selecting this Gclks or we can assign it to any GCLK,if my design as only one GCLK.
Regards,
Vinod Kumar.
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FvM
Joined: 22 Jan 2008
Posts: 2632
Helped: 431
Location: Bochum, Germany
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| 24 Aug 2008 19:45 basic doubt clock in fpga |
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| Clock signals should be preferably feed to GCLK inputs, DCM blocks must be driven by a GCLK on the same chip side (top or bottom). For a standard design without extensive DCM usage and critical timing (e.g. with DDR RAM controller), a single arbitrary choosen GCLK should be sufficient, otherwise it may be meaningful to feed a top and bottom GCLK simultanously.
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