gvsm
Joined: 10 Aug 2008
Posts: 6
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 22 Aug 2008 17:54 pls help regarding clock divider |
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hi there,
i need to know an example of a vhdl code for generating 1kHz and 10kHz wave as output. the frequency of the clock is 100kHz.
below is an example of code i did, bt there are errors where i cannot compile and run the code...
library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_unsigned.all;
use ieee.std_logic_arith.all;
entity clkdivider is
port (clkin : in std_logic;
C1, C2: out std_logic);
end clkdivider;
architecture beh of clkdivider is
--signal count : std_logic_vector (3 downto 0);
signal clk : std_logic := '0';
signal count : integer := '0' ;
begin
process (clkin,count)
begin
if (clkin'event and clkin = '1') then
count <= count + 1;
elsif (count =10) then
count <= '0';
end if;
if count<3 then
C1 = '1';
else
C1 = '0';
end if;
if count<7 then
C2 = '1';
else
C2 = '0';
end if;
end process;
end beh;
thank you.....[/code]
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